Non-volatile memory devices, and particularly FLASH memory devices, rely upon sense amplifiers to ascertain the programming state of the various memory cells by sensing a change, if any, in either a bitline voltage or current during a read or verify operation. In order to provide a reasonable noise margin, a bitline bias (of approximately 1.0V) is applied to the bitline prior to the initiation of the read/verify operation. Typically, the bitline voltage is generated by a bitline bias voltage generator circuit, which includes a current source that generates a pre-determined current IREF (IREF may be on the order of 10 μA) using a charge pump to provide the necessary supply voltage VDD (generally 5V).
Typical charge pumps are not very efficient, and consequently, the charge pump may consume a current of much greater than that of 10 uA from the chip power supply in order to provide an IREF of only 10 μA. Therefore, as a result of the large number of bitlines in a typical FLASH memory device (on the order of 128K), the charge pumps used to generate the bitline bias voltages alone can account for up to 15% of the total power requirement of the FLASH memory device.
Therefore, what is desired is an apparatus that provides power efficient control a bitline bias voltage.